Substrates with dense fine-pitch metallization and through-substrate vias have been explored for a variety of applications, including silicon interposers for use in high-bandwidth density communication between heterogeneous integrated circuits (ICs). Silicon interposers, for instance, provide an ability to integrate a variety of micro-electronic structures, such as integration of through-silicon vias to enable a variety of electronic functions and in some instances improve electrical performance. For the integration of more functionality in substrates, large-area silicon interposers are desired. Greater silicon thickness (larger than 300-400 μm) is desired as well for large-area interposers to minimize warpage and bow and improve mechanical stability. However, increasing substrate thickness can result in increased via length, leading to increased via capacitance and radio frequency (RF) losses. Conventionally, to combat this issue, high-resistivity silicon has been used. However, high resistivity silicon is expensive as compared to low resistivity silicon. In addition, the mismatch between the coefficient of thermal expansion (CTE) for copper and silicon can result in high through substrate via stresses. These factors drive the need for low-loss via technologies for large-area, thick interposers to compensate for this increased length while minimizing production cost.
To address these issues, polymer-enhanced, photo-defined electrical and optical through substrate vias have been proposed, including polymer-clad through-substrate vias and polymer-embedded through-substrate vias. Including a photodefineable polymer coating the through substrate via can decrease through substrate via capacitance and RF losses, which often plague previous high aspect ratio materials. Yet, known substrates having photo-defined through substrate vias were restricted to specific fabrication processes and lacked customizability needed to support a variety of applications, such as mixed-signal interposers.